Description
type positive-edge-triggered flip-flops. A low level at. Outputs Can Drive Up To 10 LSTTL Loads the preset (PRE) or clear (CLR) inputs sets or resets. Low Power Consumption, 40- A Maximum ICC the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data. Typical tpd = 15 ns. Jan 1, 2014 22uF Tant. Micro SD. +5V. 0V. 0.1uF. 0V. MCP23017SP. +5V. +5V. 0V. 0.1uF. C lo ck. 0V. +. 3. V. 3. +5V. +12V. LM3940. 8255. 0.1uF. 8255. 0V. To_D9_M. 5V_P25. +5V. MOUNT-HOLE3.6. MOUNT-HOLE3.6. 74HC74N . 74HC74N . +5V. +5V. 0.1uF. S lo w. _. C lo ck. +5V. 0V. 2K7. 2K7. 2K7. 2K7. 2K7. 2K7. Figure 3 shows how noise affects a 74HC74s clock input. Again, no logic errors occur with 2V or more clock noise. 54HCT/74HCT ICs have an input buffer specially designed to yield TTL input levels of 0.8 and 2V. Their noise-immunity characteristics are therefore substantially different from those of 54HC/74HC devices. Pin and function compatible with 74HC74 . General Description. The VHC74 is an advanced high speed CMOS Dual. D-Type Flip-Flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the. CMOS low power dissipation.
Part Number | 74HC74N |
Brand | Fairchild |
Image |
74HC74N
FARCHILD
12500
1.53
ONE SHIELD ELECTRONICS LIMITED
74HC74N
FAIRCH
233
2.245
Shenzhen XinShiJi Trading Co., Ltd
74HC74N
FAIRCHILP
20680
2.96
ZHONGGANG TECHNOLOGY (HK) INDUSTRY LIMITED
74HC74N
FARICHILD
50
3.675
Semitech Inc
74HC74N
FAIRCHLD
1030
4.39
FLOWER GROUP(HK)CO.,LTD